Logic circuits are operated by a clock signal provided by an oscillator. A power-on reset circuit is generally connected to the logic circuits. The power-on reset circuit provides a reset signal for the logic circuits until the power supply voltage reaches a predetermined level.
A prior art power-on reset circuit has a capacitor and a resistor for setting a time constant. A resistor having a certain resistance is connected in series with the capacitor between a power supply terminal and ground. An inverter which provides a reset signal for the logic circuit, is connected to the logic circuit and a node N which is located on a connecting point of the resistor and the capacitor.
When the power supply voltage is applied to the power supply terminal, the logic circuit and the resistor are provided with the power supply voltage, and the logic circuit receives a clock signal from an oscillator. At the same time, the node N is at the "L" level because the capacitor does not have enough charge. Accordingly the inverter inverts the "L" level signal to a "H" level signal, that is, a reset signal. The logic circuit therefore is reset by the reset signal.
Then, the capacitor is charged by electrons from the power supply terminal via the resistor, and the electrical potential of the node N becomes to rise. When the electrical potential of the node N becomes higher than a threshold voltage Vt of the inverter, the inverter output the "L'" level signal. Therefore, the reset condition of the logic circuit is canceled. The logic circuit then starts to operate in response to the clock signal.
The reset period of the reset circuit is defined by the time constant, which is from the moment of applying the power supply voltage to the power supply terminal to the moment of canceling the reset condition of the logic circuit. The time constant depend on the product of the resistance of the resistor by the capacitance of the capacitor.
The prior art power-on reset circuit, however, has some problems as follows;
(1) The resistance and the capacitance are required to be approximately a few M.OMEGA. and 0.1 .mu.F respectively if the power-on reset circuit is to have a satisfactory reset period. If a capacitor having a capacitance of 0.1 .mu.F is formed on a semiconductor substrate, it occupies a large area of the semiconductor substrate. PA1 (2) The logic circuit is operated in response to the clock signal which is generated in an internal or an external oscillator circuit. It sometimes occurs that the logic circuit does not receive the clock signal for some reasons in spite of applying the power supply voltage to the power supply terminal. In the prior art power-on reset circuit, since the reset signal is canceled after a predetermined period, another reset signal must be provided for the logic circuit to reset the logic circuit after a clock signal is applied to it. The circuit is complicated in that another reset signal is provided for the logic circuit after the clock signal is applied to it. PA1 (a) a differentiator circuit connected to the oscillator for differentiating a clock signal from the oscillator to generate a first output signal, PA1 (b) a sample-hold circuit connected to the differentiator circuit for sampling and holding the first output signal to generate a second output signal, and PA1 (c) a reset signal generating circuit having a predetermined threshold voltage connected between the sample-hold circuit and the logic circuit for generating the reset signal until an electric potential of the second output signal exceeds the threshold voltage thereof. PA1 (a) an oscillator for starting to generate a clock signal when a power supply voltage is applied thereto, PA1 (b) a differentiator circuit for receiving and differentiating the clock signal from the oscillator, PA1 (c) a sample-hold circuit connected to the differentiator circuit for sampling and holding an output from the differentiator circuit, and PA1 (d) a reset signal generating circuit having a predetermined threshold voltage connected between the sample-hold circuit and the logic circuit for generating a reset signal from the time when the power supply voltage is applied to the oscillator to the time when an electric potential of the output of the sample-hold circuit exceeds the threshold voltage thereof.